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| 基于Verilog-HDL的逻辑分析卡中双向端口的设计 | |
| 引用本文： | 王海渊,常晓明,李媛.基于Verilog-HDL的逻辑分析卡中双向端口的设计[J].太原理工大学学报,2006,37(4):463-465. |
| 作者姓名： | 王海渊 常晓明 李媛 |
| 作者单位： | 1. 太原理工大学,信息工程学院,山西,太原,030024 2. 太原理工大学,计算机与软件工程学院,山西,太原,030024 3. 天津工业大学,计算机技术与自动化学院,天津,300160 |
| 摘 要： | 介绍了自行设计逻辑分析卡的系统构成,给出各个功能模块的逻辑框图。然后,从应用的角度简单介绍了ISSI公司的静态RAM芯片IS61LV256,并阐明了将其作为逻辑分析卡外部RAM的使用方法,设计了该RAM与CPLD的硬件接口。应用Verilog-HDL语言对双向(inout)端口所进行了描述,在此基础上以一个简化了的双向(inout)端口模块为例,设计了对该双向(in-out)端口的仿真方法,并给出了仿真结果。最后给出一种简易的硬件测试方法对双向(inout)端口进行测试,证明了该设计以及对其的仿真的正确性。 |
| 关 键 词： | 逻辑分析卡 硬件测试法 |
| 文章编号： | 1007-9432（2006）04-0463-03 |
| 收稿时间： | 2005-09-06 |
| 修稿时间： | 2005年9月6日 |
Design of Bidirectional Port Based on Verilog-HDL in Logic Analysis Card |
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| WANG Hai-yuan,CHANG Xiao-ming,LI Yuan-yuan.Design of Bidirectional Port Based on Verilog-HDL in Logic Analysis Card[J].Journal of Taiyuan University of Technology,2006,37(4):463-465. | |
| Authors: | WANG Hai-yuan CHANG Xiao-ming LI Yuan-yuan |
| Institution: | a. College of Information Engineering of TUT, Taiyuan 030024, China; b. College of computer software of TUT, Taiyuan 030024 ,China ; 3. College of computer techniqe and automatization of TJPU, Tianjin 300160, China |
| Abstract: | This paper firstly introduced the systemtic composition of logic analysis card,which is designed independently,and attached the logic frame diagram of each module.Then from application angle,it also illustrated the static state RAM chip IS61LV256 produced by ISSI,and how to use this chip for the external memory storage of logic analysis card.Hardware interface between this RAM and CPLD was designed,which was described and emulated by Verilog-HDL.Finally,a kind of simple hardware test method was given,to justify the correctness of this design and emulation. |
| Keywords: | Verilog-HDL inout RAM |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |