基于元编程技术的硬件设计模式研究

针对硬件设计的复杂性和自动化效率低等问题,提出了一种基于时钟处理的硬件设计模式．该模式充分考虑了软、硬件模式设计的互通性,并结合元编程技术,将成熟的软件设计模式的思路应用于硬件设计之中．它的核心是：用高速集成电路硬件描述语言（VHDL）解析器分析已知器件的接口,构造语法树,抽取生成器的变量值;将生成器用元程序封装在域实体之中;按照设计模式的作用和具体的变量值生成详细的VHDL代码．应用实例表明,所提模式生成的代码有效性高,设计过程可行性强,可广泛应用于复杂的时钟控制系统的设计领域．

Research on Hardware Design Patterns Based on Metaprogramming Techniques

Focusing on the problems of hardware design complexity and low efficiency,a clock signal hardware design pattern based on metaprogramming techniques is proposed,in which the interoperability between software and hardware design patterns is considered sufficiently and the(idea) of mature software design pattern is applied to the hardware design combined with metaprogramming techniques.The core of the proposed design pattern is to use the parser of VHDL(very high speed integrated circuit hardware description language) to analyze the known device interfaces,construct a syntax tree,extract variable values of generator which is wrapped in a domain entity using metaprograms,and the detailed VHDL code is therefore generated according to the design pattern and concrete variable values.Application examples show that the code generated by the proposed design pattern has high validity and strong feasibility in the design process,and can be applied widely to designing of complicated clock signal control systems.