GPS/INS超紧组合系统载波相位跟踪误差研究

载波跟踪环(PLL)设计是GPS接收机设计中的关键问题，PLL的相位误差源包括相位抖动和动态应力误差.随着接收机工作平台动态性的增加，较大的动态应力误差将导致环路失锁.为适应高动态环境，GPS接收机通常采取INS辅助GPS跟踪环路的超紧组合方式来降低动态应力误差.组合系统提供的外界辅助信息不可能完全精确，所以跟踪环路在减小动态应力误差时，也会引入其他测量误差源.对GPS/INS超紧组合系统PLL跟踪误差进行了详细推导并且得出两个解析公式.仿真结果表明，对超紧组合系统的PLL跟踪误差公式推导是准确的，为PLL环路参数的最优设计提供理论参考.

Research on Carrier Phase Tracking Error in Ultra-tightly Coupled GPS/INS Integration

The design of carrier phase lock loop(PLL)is a key technology in the design of GPS receiver. The main error sources of PLL include phase jitter and dynamic stress error. With the increase of receiver platform dynamic， the larger dynamic stress error will lead to the loop loss lock. In order to adapt to the dynamic environment， the receiver usually use ultra-tightly coupled(UTC) GPS/INS integration with INS aided PLL tracking loops. Due to the aided information which the integration system provided may not be completely accurate， the tracking loop can reduce the dynamic stress error and will also introduce other measurement error sources. The PLL tracking error based on the INS estimation Doppler error was deduced in detail and two specific formulas were obtained. The simulations results showed that the PLL tracking error analysis were accurate on UTC system， which could provide reference for the optimal design PLL loop parameters.