Design and implementation of a high-speed reconfigurable cipher chip

1. INTRODUCTION For present requirements on network or others security systems, cipher chips are expected to support multi-algorithms and flexibility becomes more and more important. Most cryptographic algorithms have similar basic operations which can be designed as RPUs (Reconfigurable Processing Units). By control- ing of some controllable nodes, RPUs can be reconfig- ured to construct different circuits and can implement different functions to match different algorithms quickly and…

Design and implementation of a high-speed reconfigurable cipher chip

A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfiguration analysis of algorithms, the design of reconfigurable processing units and a new reconfigurable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the operating frequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.