| 基于74LS192的任意进制加法计数器的设计 |
| |
| 引用本文： | 穆玉珠.基于74LS192的任意进制加法计数器的设计[J].西南民族大学学报(自然科学版),2017,43(6):599-602. |
| |
| 作者姓名： | 穆玉珠 |
| |
| 作者单位： | 西南民族大学 电气信息工程学院 |
| |
| 基金项目： | 西南民族大学2015年教改项目,2015QN09 |
| |
| 摘 要： | 74LS192是一种双时钟集成十进制同步可逆计数器,是数字系统设计中常用的器件.分别用反馈归零法、反馈置数法以及进位输出端设计了基于74LS192的小容量任意进制加法计数器,并用反馈归零法设计了一种计数长度为68的大容量加法计数器.介绍的设计方法对广大电子爱好者设计相关计数器具有很好的指导意义.
|
| 关 键 词： | 计数器 74LS192 数字电路 |
| 收稿时间： | 2017/5/19 0:00:00 |
| 修稿时间： | 2017/11/15 0:00:00 |
Design of Mulitinary Up-counter Based on 74LS192 |
| |
| MU yuzhu.Design of Mulitinary Up-counter Based on 74LS192[J].Journal of Southwest University for Nationalities(Natural Science Edition),2017,43(6):599-602. |
| |
| Authors: | MU yuzhu |
| |
| Institution: | Southwest University For Nationalities |
| |
| Abstract: | As a double-clock integrated decimal reversible counter, 74LS192 is the common device in digital systems. In this paper, small capacity mulitinary up-counters based on 74LS192 are designed by the methods of feedback- zeroing, feedback-loading and carry out terminal, and one big capacity up-counters(68-module) is also designed by feedback- zeroing method here. The design methods described in this paper have great value of reference to electronics lovers to design related counter. |
| |
| Keywords: | counter 74LS192 digital circuit |
| 本文献已被 CNKI 等数据库收录！ |
| 点击此处可从《西南民族大学学报(自然科学版)》浏览原始摘要信息 |
| 点击此处可从《西南民族大学学报(自然科学版)》下载免费的PDF全文 |
