| 基于FPGA的准循环LDPC码低时延译码器设计 |
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| 引用本文： | 雷瑾亮,陈洪美,王爱华.基于FPGA的准循环LDPC码低时延译码器设计[J].北京理工大学学报,2013,33(7):732-735. |
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| 作者姓名： | 雷瑾亮 陈洪美 王爱华 |
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| 作者单位： | 中国科学院微电子研究所,北京100029;国家科技部高技术研究发展中心,北京100044;北京理工大学信息与电子学院,北京,100081 |
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| 基金项目： | 国家自然科学基金资助项目(61271258) |
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| 摘 要： | 针对准循环低密度奇偶校验码(LDPC码),提出一种基于FPGA的低延时译码器硬件实现结构. 该译码器基于最小和译码算法,充分利用FPGA的RAM存储结构及流水线运算方式提高译码吞吐量,降低译码时延. 该结构适用于大部分准循环LDPC码,且译码迭代一次只需约2倍缩放因子大小的时钟数量. 与非流水线译码结构相比,在不增加资源占有率的情况下,译码时延降低到原来的1/7.
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| 关 键 词： | 准循环LDPC码 低时延译码 FPGA实现 流水线 |
| 收稿时间： | 2012/7/23 0:00:00 |
Low-Latency Decoder for Quasi-Cyclic LDPC Codes Based on FPGA |
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| LEI Jin-liang,CHEN Hong-mei and WANG Ai-hua.Low-Latency Decoder for Quasi-Cyclic LDPC Codes Based on FPGA[J].Journal of Beijing Institute of Technology(Natural Science Edition),2013,33(7):732-735. |
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| Authors: | LEI Jin-liang CHEN Hong-mei and WANG Ai-hua |
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| Institution: | 1.The Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;High Technology Research and Development Center of the Ministry of Science and Technology, Beijing 100044, China;2.School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China |
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| Abstract: | A hardware architecture scheme of low-latency decoder for quasi-cyclic LDPC (QC-LDPC) codes is proposed using Min-Sum decoding algorithm. It takes the advantages of configurable embedded memory in FPGA and pipelining operational mode to improve the throughput of a decoder for QC-LDPC codes. The decoding time complexity is only about 2 times the size of the zoom factor of quasi-cyclic parity check matrix. Compared with non-pipelining decoding structure, the decoding latency is reduced to the original 1/7 without increasing logical resources. |
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| Keywords: | quasi-cyclic LDPC low-latency decoder FPGA implementation pipelining |
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