结合奇偶测试的大规模集成电路征兆测试

征兆测试是一种高效简捷的电路测试方法。该文提出一种适用于大规模集成电路的测试方法——组合征兆测试法。利用这种方法,测试者可以通过穷举输入组合,使奇偶测试和征兆测试相结合,共同解决对大规模集成电路故障测试的难题。主要思想是:首先通过被测电路的奇偶性判断该电路的征兆测试法的可测性,对征兆测试法不可测的电路,引入高阶征兆测试的思想,使其成为高阶征兆测试法可测电路。结果表明:该方法在提高可测性的同时,还提高了电路征兆测试的测试效率和故障覆盖率。通过对一些基准电路和常用电路的测试验证了该方法的实用性。

Combined parity testing for syndrome testing of VLSI circuits

Syndrome testing has been recognized as an effective way to test very large scale integrated(VLSI) circuits.A parity syndrome testing method was developed based on a combination of parity and syndrome tests to improve the effectiveness and testability of VLSI circuit tests.The function under test is first checked to determine the syndrome testability using parity checking,and then the circuit is tested using syndrome testing if syndrome testable or using high order syndrome testing if not syndrome testable....