一种基于RCRF+BCH算法的NAND FLASH纠错方案的FPGA设计与实现

针对可见光图像和红外图像的融合目标检测问题，提出了一种基于决策级融合的目标检测算法。通过建立带标注的数据集对YOLOv3网络进行重新训练，并在融合之前，利用训练好的YOLOv3网络对可见光图像和红外图像分别进行检测。在融合过程中，提出了一种新颖的检测融合算法，首先，保留只在可见光图像或只在红外图像中检测到的目标的准确结果；然后，对在可见光图像和红外图像中同时检测到的同一目标的准确结果进行加权融合；最后，将所得的检测结果进行合并，作为融合图像中所有对应目标的检测结果，进而实现基于决策级融合的快速目标检测。实验结果表明：各项指标在建立的数据集上均有较好的表现。所提算法的检测精度达到了84.07%，与单独检测可见光图像和红外图像的算法相比，检测精度分别提升了2.44%和21.89%，可以检测到更多的目标并且减少了误检目标的情况；与3种基于特征级图像融合的检测算法相比，算法的检测精度分别提升了4.5%，1.74%和3.42%。

FPGA Design and Implementation of a NAND FLASH Error Correction Scheme Based on RCRF + BCH Algorithm

Aimed at the characteristic that the error rate of NAND FLASH increases with the increase of the time of use, a high speed parallel RCRF+BCH error correction scheme with stronger error correction capability while using fewer parity bits is proposed. The idea of RCRF corrects some of the initial erasure errors, and then cascades BCH codes to correct the remaining bit errors, which can greatly ensure the accuracy of data and significantly improve the reliability of the storage system. The article explains in detail the encoding and decoding principles and execution steps of the high speed parallel algorithm. In the BCH part, the iBM key equation solving algorithm without inversion that consumes less hardware resources is used, and then the different paths of the error position polynomial are listed through derivation Several-deterministic forms facilitate the application of combinatorial logic to describe them, thus avoiding the complicated iterative judgment process and further improving the decoding speed. And adopt the modular processing method and the pipeline operation mode to optimize the BCH codec structure. Finally, it was implemented on FPGA platform hardware and simulated to verify the effectiveness of this scheme.