| 高性能2．5Gbps PCI Express并串转换电路的设计 |
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| 引用本文： | 黄佳.高性能2．5Gbps PCI Express并串转换电路的设计[J].广西师院学报,2009(3):55-59. |
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| 作者姓名： | 黄佳 |
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| 作者单位： | 广西师范学院物理与电子工程学院,广西南宁530023 |
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| 摘 要： | 并串转换电路作为PCI Express物理层（PHY）发送端的重要模块之一，将来自PCS（Physical coding sublayer）子层的10bit并行数据转换成1bit串行数据．该文提出并实现了一种高性能并串转换电路，采用0．18μm工艺版图实现，反标寄生参数后使用spice进行仿真，仿真结果证明该电路可在1．0GHz～1．5GHz稳定工作，其最高数据传输速度达到3Gbps，完全达到了预期效果．
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| 关 键 词： | 并串转换 半速率时钟 双沿移位 移位寄存器 PCI Express |
The Design of 2.5Gbps High Speed Serializer for PCI Express |
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| HUANG Jia.The Design of 2.5Gbps High Speed Serializer for PCI Express[J].Journal of Guangxi Teachers College(Natural Science Edition),2009(3):55-59. |
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| Authors: | HUANG Jia |
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| Institution: | HUANG Jia (Department of Physics and Electronic Information Science, Guangxi Teachers Education University, Nanning 530023, China) |
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| Abstract: | As an important part of the PHY（Physical Layer） in PCI Express, the high Speed Serializer transmits the 10bit parallel data into 1bit serial data. A new type of serializer with high performance for PCI Express is presented in this paper, which reaches the bandwidth of 2.5Gbps, realized with full CMOS technics, and is compatible with the features of PCI Express. When designed with 0.18μm CMOS technology, extracting parameters from the layout for SPICE simulation, it indicates that the circuit works nice with the acceptable frequency ranges from 1.0GHz to 1.5GHz and the bandwith up to 3Gbps. |
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| Keywords: | serializer half rate clock dual edge shifting shift register PCI express |
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