| VLIW体系结构微处理器功能验证模型 |
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| 引用本文： | 王沁. VLIW体系结构微处理器功能验证模型[J]. 北京科技大学学报, 2002, 24(4): 458-462. DOI: 10.3321/j.issn:1001-053X.2002.04.020 |
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| 作者姓名： | 王沁 |
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| 作者单位： | 北京科技大学信息工程学院,北京,100083 |
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| 基金项目： | 国家高技术研究发展计划(863计划);863-306-01-07; |
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| 摘 要： | 为了系统而有效地设计微处理器功能验证激励,针对VLIW体系结构微处理器的结构特征,特别是多操作流水线并行特征,提出了VLIW体系结构微处理器的功能验证模型,基于该模型, 针对一个规模为1 500 kbit等效逻辑门的VLIW体系结构微处理器, 完成了功能验证方案的制定和105周期功能验证激励的设计.
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| 关 键 词： | 字 VLIW 微处理器 功能验证 模型 |
| 修稿时间： | 2001-05-14 |
VLIW Architecture Microprocessor Functional Verification Model |
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| WANG QinInformation Engineering School,UST Beijing,Beijing ,China. VLIW Architecture Microprocessor Functional Verification Model[J]. Journal of University of Science and Technology Beijing, 2002, 24(4): 458-462. DOI: 10.3321/j.issn:1001-053X.2002.04.020 |
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| Authors: | WANG QinInformation Engineering School UST Beijing Beijing China |
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| Affiliation: | WANG QinInformation Engineering School,UST Beijing,Beijing 100083,China |
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| Abstract: | When the architecture and organization of microprocessor is becoming more and more complex, the problem about how to verify the microprocessor function is becoming more and more important. In order to design the functional verification stimulus of microprocessor effectively, a functional verification model of VLIW architectural processor is introduced, based on the organization characteristic, especially the parallel pipeline, in the VLIW microprocessor. Based on the verification model, a verification schema and 100,000 cycle of stimulus for a VLIW microprocessor design have been finished, which includes about 1500 Kbit gates. |
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| Keywords: | VLIW microprocessor functional verification model |
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