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高性能密码服务器的并行数据处理
引用本文:容晓峰,苏锐丹,刘平,周利华.高性能密码服务器的并行数据处理[J].系统工程与电子技术,2005,27(6):1115-1119.
作者姓名:容晓峰  苏锐丹  刘平  周利华
作者单位:1. 西安电子科技大学计算机网络与信息安全教育部重点实验室,陕西,西安,710071;西安工业学院计算机科学与工程学院,陕西,西安,710032
2. 西安电子科技大学计算机网络与信息安全教育部重点实验室,陕西,西安,710071
3. 国家信息安全工程技术研究中心,北京,100093
基金项目:国家"十五"重点科技攻关项目基金资助课题(2002BA103A04)
摘    要:随着大型电子商务和电子政务系统中客户数量的增多,主机端密码系统的性能成为提供安全服务的限制因素。提出了一种基于可编程密码模块的密码服务器体系结构。通过在模块中使用密码算法代理抽象密码芯片运算资源,管理机可以调度系统计算资源支持多模块内多密码芯片间的并行密码运算。在IBMService345和SJW系列PCI密码卡上,设计实现了基于算法代理间并行运算的高性能密码服务器。测试结果显示:用20个SSX04模幂运算芯片间并行签名(1024 bitRSA)速率达到1100次/s;用10个对称密码算法芯片并行加密(ECB模式),系统吞吐率达到312.6Mbps。

关 键 词:密码芯片  密码模块  密码服务器  吞吐率  并行处理
文章编号:1001-506X(2005)06-1115-05
修稿时间:2004年6月20日

Parallel data processing of high-performance cryptographic co-server
RONG Xiao-feng,SU Rui-dan,LIU Ping,ZHOU Li-hua.Parallel data processing of high-performance cryptographic co-server[J].System Engineering and Electronics,2005,27(6):1115-1119.
Authors:RONG Xiao-feng  SU Rui-dan  LIU Ping  ZHOU Li-hua
Institution:RONG Xiao-feng~
Abstract:With more and more clients attached to a host, performance of cryptographic operations at the host has become a constraint that prevents the achievement of acceptable secure services at large e-commerce and e-governments. A cryptographic co-server architecture based on the programmable secure crypto modules is presented. By using crypto algorithm agents to abstract computation resource of crypto chips in modules, the crypto-manager can schedule system resources to support parallel data processing among crypto chips in crypto modules. Based on an IBM Services345 machine and series of SJW PCI crypto cards, the high-performance cryptographic co-server was designed and implemented by carrying cryptography computations in parallel among crypto algorithm agents. The test results indicate that: when computation in parallel among 20 SSX04 chips, the performance of generate 1024 -bit RSA digital signature is 1 100 operations per second; when computation in parallel among 10 symmetric chips, the throughput of encryption (ECB mode) was 312.6Mbps.
Keywords:crypto chip  crypto module  cryptographic co-server  throughput  parallel process
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