一种环形网络的可扩展流水仲裁器设计

对环形网络的仲裁器结构进行研究,提出了一种可扩展流水仲裁器结构,能够同时完成通信缓冲和通信链路的分配.对14个通信节点互连进行了建模模拟,各节点命中数量差值小于5%,该结构仲裁器具有较好的仲裁公平性;然后采用Chartered 65nm工艺对RTL设计进行了时序综合实验,关键通路延迟比同等规模的全交叉开关结构降低36.8%;同时该仲裁结构中的仲裁核心逻辑时序受互连规模变化影响较小,具有一定的可扩展性.

A Scalable Pipelined Arbiter Design for Ring Bus

The arbiter architecture of the ring bus was studied, and a novel extensible pipelined design was proposed, which can allocate the communication buffers and links simultaneously. Three characteristics have been found in the proposed design. Firstly, the arbiter is fair for each node, only with a 5% difference of the hit number. The communicated nodes were found in the simulation when the arbiter in an interconnect system was modeled with 14 nodes. Secondly, compared with the crossbar design, the worst time delay of our synthesis RTL design with Chartered 65 nm Technology was reduced by 36.8%. Furthermore, as the number of the nodes has less effect on the key circuit, the arbiter has certain scalability.