低抖动高线性压控振荡器设计与仿真分析

设计一种应用于锁相环(PLL)电路的压控振荡器(VCO).该电路采用浮空电容结构,相对传统接地电容结构,可提高电容充放电幅值,减小时钟抖动.快速电平检测电路,使电路在未采用反馈和补偿的前提下,减小环路延时,从而实现高线性.电路采用CSMC 0.6 μm CMOS标准工艺库实现.仿真结果表明:振荡频率为0.79,24,30 MHz时的相位噪声达到-128,-122,-120 dBc·Hz^-1@1 MHz.通过调节外接电阻电容,使得电路在3~6 V电源电压下,输出100.0~3.0×10⁷ MHz的矩形波,电路兼具低相位噪声和高线性特性.

Design and Simulation Analysis of Low-Jitter High-Linearity Voltage-Controlled Oscillator

A voltage-controlled oscillator(VCO)was designed for phase-locked loop(PLL). Floating timing capacitor architecture was adopted to enhance amplitude of capacitor’s charge and discharge, compared with grounded timing capacitor architecture, reducing the clock jitter. The rapid level detection circuit, which reduced the loop delay and achieves high-linearity without using feedback and compensation. The circuit was designed in CSMC 0.6 μm CMOS process. Simulation results showed that the phase noise was -128, -122, -120 dBc·Hz^-1@1 MHz when the oscillation frequency was 0.79, 24, 30 MHz. The circuit output 100.0~3.0×10⁷ Hz square wave at 3~6 V supply voltage by adjusting the external resistor and capacitor. The characters of this circuit were not only low phase noise but also high-linearity.