| 4个加数的并行加法器及扩展接口的研究 |
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| 引用本文： | 刘杰,易茂祥.4个加数的并行加法器及扩展接口的研究[J].合肥工业大学学报(自然科学版),2009,32(11). |
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| 作者姓名： | 刘杰 易茂祥 |
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| 作者单位： | 1. 合肥工业大学,电子科学与应用物理学院,安徽,合肥,230009;阜阳师范学院,物理与电子科学学院,安徽,阜阳,236041
2. 合肥工业大学,电子科学与应用物理学院,安徽,合肥,230009 |
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| 基金项目： | 安徽省高校省级自然科学研究资助项目 |
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| 摘 要： | 算术逻辑运算单元(ALU)决定着中央处理器(CPU)的性能,而加法器又决定着ALU的性能.为了提高CPU的性能,文章提出了一种4个加数的并行加法器及其接口扩展的研究方案,论述了所提新型加法器的工作原理和过程,同时描述了接口扩充思想;最后,采用MAX+PLUSⅡ对设计电路进行了模拟验证,实验结果说明了所提加法器的设计合理性.
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| 关 键 词： | 算术逻辑运算单元 加法器 超前进位加法器 |
Research on a parallel adder with 4 binary addends and its interface |
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| LIU Jie,YI Mao-xiang.Research on a parallel adder with 4 binary addends and its interface[J].Journal of Hefei University of Technology(Natural Science),2009,32(11). |
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| Authors: | LIU Jie YI Mao-xiang |
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| Abstract: | The arithmetic logic unit(ALU) decides the performance of the Central Processing Unit (CPU) , while the adder decides that of the ALU. To improve the performance of the CPU, a parallel adder with 4 binary addends and its interface are proposed. The working principle and process of the novel adder are discussed, and its interface extension is described. Finally,the MAX+PLUS II is a-dopted to simulate and validate the proposed adder. Experimental results indicate that the proposed design scheme is not only reasonable, but it can also calculate 4 binary addends faster than a carry look-ahead adder using the serial adding scheme. |
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| Keywords: | arithmetic logic unit adder carry look-ahead adder |
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