基于复用测试逻辑方法的集成电路硅调试设计方案

提出了一种集成电路芯片的硅调试设计方案.采用具有短链扫描结构的扫描链复用方法，以提高对芯片触发器类信息的读写速度，为存储器内建自测试（MBIST）控制器增加异步通信调试接口，以提高静态存储器类信息的访问速度，同时，简化了MBIST控制器的物理设计难度.结果表明，所提出的硅调试设计方法可以降低硬件资源的消耗，使得调试软件设计的难度和复杂度显著降低，并使得硅调试的相关操作更加简便.

Design for Silicon Debug of Integrated Circuit by Reusing Test Logic

Test logic is often reused by silicon debug during design stage of IC. Based on reusing test logic, two improved structures for silicon debug were proposed, one is that scanning registers in short chains to speedup accesses of focused registers, another is that adding asynchronous debug ports for memory build-in self-test (MBIST) controller, which accelerates accesses of static memory and reduces difficulties of physical design. The experiment reflects that the proposed structure decreases difficulty and complexity of the corresponding software extremely at little extra resources cost, and makes debug operations faster.