一种面向三维微处理器的新型片上网络拓扑

利用三维集成电路中硅通孔具有延迟短、功耗低的特性，针对10层以上硅片堆叠的三维片上网络，设计了一种新的拓扑结构3DE Mesh，并通过实验数据的分析，验证了3DE Mesh的性能和可扩展性.结果表明，3DE Mesh的性能和可扩展性均满足10层以上硅片堆叠的三维集成电路的要求.

A Novel Networks-on-Chip Topology for Three Dimensional Microprocessor

By utilizing silicon via’s characteristics such as short delays and less power consumption, this paper designed a new kind of topology 3DE-Mesh for a three dimensional networks-on-chip which has more than 10 layers of stacked dies. By analyzing the experimental data the paper proves 3DE-Mesh’s function and scalability. The simulation results indicate that the 3DE-Mesh satisfies the requirements of the three dimensional integrated circuits which has more than 10 layers of stacked dies.