采用时钟屏蔽策略降低测试功耗

为了降低每时钟周期的平均及峰值功耗,在两级扫描结构基础之上提出时钟屏蔽及它的改进策略。利用测试激励压缩条件和测试响应压缩条件对电路进行划分,在每个时钟周期激活子电路的方法来降低峰值。实验结果表明:采用改进策略测试的总功耗平均降低到全扫描的0.39%,峰值功耗平均降低到全扫描的16.26%,捕获阶段的峰值平均降低到全扫描的10.97%。从结果可以看出,采用多级时钟屏蔽策略进行电路测试,与传统的全扫描测试方法相比,测试功耗及其他影响扫描测试代价的参数均有明显的降低。

Clock-disabling scheme to reduce test power

A two-stage clock disabling architecture was developed to reduce average and peak power level during digital circuit testing.The circuit under test(CUT)is partitioned according to the test stimulus compression condition and the test response compression condition with only sub-circuits activated in each clock cycle to reduce peak power.The experimental results show that the total power is reduced to 0.74% that of the traditional full scan scheme,peak power is reduced to 18.41%,peak power in the capture stage is reduced to 11.32%.Hereby,the test power and other factors related to the test application cost are greatly reduced compared with the traditional full scan scheme.