AES快速算法的扩展指令集实现

基于Daemen等提出的AES快速算法,给出了用可配置处理器NiosII扩展指令集实现硬件加速的两种方案——基于片内存储器存储快速算法查找表的方法、用硬件逻辑电路实现S盒并计算出快速算法查找表对应元素的方法,用对前向查找表的查表操作代替了AES算法计算密集的轮变换操作.首先,将快速算法的前向查找表存放在片上内存中,并用12条扩展指令分别完成密钥扩展、轮变换和末轮操作,末轮变换所需的S盒采取对前向查找表的掩模得到;然后,对该方案进行优化以消除片上内存的占用,即推导出S盒与前向查找表的逻辑关系,并采取有限元素求逆的方法用逻辑电路实现S盒,增强了系统安全性并降低了功耗;最后,对扩展指令集和协处理器等多种实现方案进行了测试及性能对比.结果表明,相比于经过结构优化的纯软件快速AES算法,文中提出的方案在仅增加223个LE的条件下,达到了2.47倍的加速比.

Implementation of Extended Instruction Set for AES Fast Algorithm

Based on Daemen’s AES fast algorithm,two schemes of implementing the instruction set extension on configurable processor NiosII are proposed to achieve hardware acceleration.These two schemes,one of which stores lookup table in on-chip memory and the other uses a logic circuit to realize the S-box and calculates the co-rresponding elements of the lookup table,employ a forward lookup table to replace the intensive round transformation operation.Specifically,the forward lookup table of the fast algorithm is placed in on-chip memory,12 new extended instructions are created to achieve the key expansion,the round transformation and the last round transformation,and the S-box used in the last round is obtained by masking the forward look-up table.In order to eliminate the on-chip memory usage,the schemes are then optimized by deriving the logical relationship between the S-box and the forward lookup table and by employing a logic circuit to realize the S-box via the inverse finite element method.Thus,the system security is enhanced and the power consumption is reduced.Finally,the performances of the extended instruction sets,the coprocessor and some other schemes are tested and compared.The results show that,as compared with the pure software solution of AES fast algorithm with optimized structure,the proposed schemes increase the speedup by 247% only with 223 additional LEs.