A 14.5Gb/s word alignment circuit in 0.18μm CMOS technology for high-speed SerDes |
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引用本文: | 阮伟华 Hu Qingsheng.A 14.5Gb/s word alignment circuit in 0.18μm CMOS technology for high-speed SerDes[J].高技术通讯(英文版),2014,20(3):328-332. |
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作者姓名: | 阮伟华 Hu Qingsheng |
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基金项目: | Supported by the National High Technology Research and Development Programme of China ( No. 2011AAI0305 ). |
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摘 要: | This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabricated in 0.18μm CMOS technology with total area of 1.075 ×0.775mm~2 ̄ including I/O pad.Measurement results show that this circuit achieves the maximum data rate of 14.5Gb/s,while consuming a total power of 34.9mW from a 1.8V supply.
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关 键 词: | CMOS技术 电路实现 解串器 对齐 串行 流水线结构 优化技术 设计方法 |
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