扫描与边界扫描电路延迟故障的测试

本文提出了一种用于扫描通路与边界扫描易测试设计电路中锁存器的排序算法，通过减小锁存器的相关性来提高通路延迟故障的被测度。该算法已在Ａｐｏｌｏ工作站用ＤＯＭＡＩＮＣ语言实现。延迟故障模拟实验表明，排序电路同原序电路相比，其延迟故障被测度明显提高

Delay Fault Test in Boundary Scan and Scan Path Architectures

An algorithm determing an efficient arrangement of latches in the boundary scan and scan path design for testability is addressed in this paper. Path delay fault coverage can be improved by reducing the correlation of neighboring latches. The algorithm introduced in the paper has been implemented on a Apollo Workstation using DOMAIN C programming language. Experimental results of the delay fault simulation indicate that the algorithm clearly achieves better fault coverage than original scan path.