超低介电常数材料和多孔SiOCH薄膜

集成电路的特征尺寸将降低到0．1μm，这时器件内部金属连线的电阻和绝缘介质层的电容所形成的阻容造成的延时、串扰、功耗已经成为限制器件性能的主要因素。目前集成电路的金属连线价质层材料为铝／二氧化硅配置，用电阻更小的铜取代铝作金属连线，用低介电常数(低K)材料取代二氧化硅作介质层成为科学意义重要、应用价值巨大的研究课题，微电子器件正经历着一场材料的重大变革中。本文着重评述了纳米尺度微电子器件对低介电常数(低k)薄膜材料的要求，介绍了多孔硅基低k薄膜的研究进展。

Ultra-low Dielectric Constant Materials and Porous SiOCH Films

The device feature size of ULSI will decrease to 100nm in few years. Smaller transistors work faster, so Ics have become faster and more complex. An emerging factor that may disrupt this trend is the slowing speed of signal propagation within the chips. Signal delay, caused by the resistance and capacitance between the wires, increase with each generation of scaling and may soon limit the overall performance of the integrated system. The introduction of Cu and low k dielectrics has incrementally improved the situation as compared to the conventional Al/QX(Y10] SiO 2 system. This review is an attempt to give an overview of requirements for low k dielectrics materials and developments of research on porous QX(Y10] SiOCH films with ultra low k.