基于BIST方法的新型FPGA芯片CLB功能测试方法

新型FPGA普遍使用了6输入查找表以实现可编程逻辑,如Xilinx公司的Virtex 5系列、Ultrascale系列等.由于I/O数量有限,针对这些芯片的CLB功能测试,可选择ILA级联测试法并利用位流回读进行故障定位,但由于CLB存在路径互斥,覆盖所有故障所需配置较多,而位流回读较为缓慢,限制了定位速度.BIST测试法通过直接检测CLB的输出来发现故障,所需配置数量少于ILA级联法,但需要将测试激励传递到所有BUT导致端口负载大,布线存在困难.本文提出了一种将ORA中闲置资源配置为锁存器链,以便传递测试激励的方法.该方法降低了端口负载.同时利用剩余的逻辑资源建立扫描链,大幅加快了故障定位速度.在Xilinx 7系列FPGA上的实验结果表明,与其他文献所用测试方案比较,测试所需配置次数由30次降低到26次,故障定位所需时间在2.4MHz时钟驱动下可达61.35ns.

A New Built-In Self-Test Method for Functional Test of Configurable Logic Blocks in Modern FPGAs

The modern FPGAs have begun to use 6-input look-up tables to perform configurable logic,such as Xilinx's Virtex-5 series,Ultrascale series and so on.Due to the limited number of IOB ports,most approaches choose the ILA based method for the functional test of these chips' CLB module,and use read-back techniques for fault isolation.Unfortunately some of the data-paths are exclusive in CLB;So ILA methods usually cost more configurations,while read-back is quite slow.The Built-In Self-Test(BIST) methods directorially check the output pins of CLBs,which reduce the number of configurations.But BIST methods should transfer test benches signals to ever BUT,which leads to massive fan-out and make it difficult to route the design.This paper presents a new BIST method which use the free resource in ORAs to form latch chains to transfer test benches.This method is able to decrease the fan-out of I/O ports.And the remaining logic resources are configured to form a scan-chain for faster fault isolation.The BIST method is tested on a Xilinx 7 series FPGA chips.Compared with the former works,the number of configurations is reduced from 30 to 26,and the cost of fault isolation is reduced to 61.35 ns with a 2.4 MHz clock.