| 实现FPGA高效动态可重配置的触发器电路 |
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| 引用本文： | 卢海舟,来金梅,童家榕. 实现FPGA高效动态可重配置的触发器电路[J]. 复旦学报(自然科学版), 2009, 48(4) |
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| 作者姓名： | 卢海舟 来金梅 童家榕 |
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| 作者单位： | 复旦大学,专用集成电路与系统国家重点实验室,上海,201203;复旦大学,专用集成电路与系统国家重点实验室,上海,201203;复旦大学,专用集成电路与系统国家重点实验室,上海,201203 |
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| 基金项目： | 国家“八六三”高技术研究发展计划资助项目(2007AA01Z285);;国家自然科学基金资助项目(60876015,60776023) |
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| 摘 要： | 设计了一种在现场可编程逻辑阵列(FPGA)内可供配置的触发器电路结构.主要特点是:不需要浪费FPGA内组合逻辑的资源,就可以独立配置出56种全部常用类型的D触发器电路或锁存器电路;以FPGA在配置简单时序电路时增加50%面积的代价降低了配置为复杂时序电路时70%的延时和90%的面积.同时针对Xilinx Virtex系列FPGA动态重配置速度较慢的缺点,在触发器电路中加入了抓捕与写回电路;提出了通过硬件电路来实现重配置状态保存和写回的方法.与Xilinx Virtex器件完全用软件实现的方法相比,加快了FPGA动态重配置电路的速度.
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| 关 键 词： | 现场可编程逻辑阵列 触发器 锁存器 动态可重配置 抓捕与写回电路 |
High Effective Dynamic Reconfigurable Registers in FPGA |
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| LU Hai-zhou,LAI Jin-mei,TONG Jia-rong. High Effective Dynamic Reconfigurable Registers in FPGA[J]. Journal of Fudan University(Natural Science), 2009, 48(4) |
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| Authors: | LU Hai-zhou LAI Jin-mei TONG Jia-rong |
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| Affiliation: | ASIC & System State Key Laboratory;Fudan University;Shanghai 201203;China |
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| Abstract: | A new type of configurable register circuit in FPGA is proposed.Without wasting combinational logic resources in FPGA,the circuit can be independently configured as 56 types of latches and D Flip-Flops.At the cost of 50% area,the proposed register reduces 70% delay and 90% area of the whole circuit when configured as a complicated sequential circuit.Meanwhile,in order to improve the slow speed in dynamic configuration for the Xilinx Virtex series,the capture and writeback circuits are also included in the p... |
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| Keywords: | FPGA register latch dynamic reconfiguration capture and writeback circuit |
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