| 一种用于PCM34.368Mb/s微波通信系统的数字锁相环 |
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| 引用本文： | 汪玲玲,孙仁琦. 一种用于PCM34.368Mb/s微波通信系统的数字锁相环[J]. 南京邮电大学学报(自然科学版), 1987, 0(4) |
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| 作者姓名： | 汪玲玲 孙仁琦 |
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| 摘 要： | 本文讨论了一种用于QPSK的解调数字锁相环在环路时延下的性能,得到了环路设计的五个约束条件。通过计算机辅助设计,得到锁相环的设计数据。制造了硬件,进行了中频自环测试,测试结果与理论值相符。
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| 关 键 词： | 微波通信系统 脉码调制 锁相环路 |
A Digital PLL Used in PCM 34.368Mb/s Microwave, Communication Systems |
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| Wang Lingling Sun Renqi. A Digital PLL Used in PCM 34.368Mb/s Microwave, Communication Systems[J]. JJournal of Nanjing University of Posts and Telecommunications, 1987, 0(4) |
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| Authors: | Wang Lingling Sun Renqi |
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| Affiliation: | Wang Lingling Sun Renqi |
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| Abstract: | This paper discusses the performances of digital PLL used in QPSK demoduIation systems under the influence of time delay. Five limited conditions for designing digital PLL are derived. By means of CAD, the design data of digital PLL are obtained. The hardware is realized and the tests for the close loop at the intermediate frequencies are made The experimental results agree with those obtained by theoretical analysis. |
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| Keywords: | Microwave Communication systems Pulse code modulation Phase locked loop |
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