| 一种嵌入式二乘二取二容错计算机联锁系统设计 |
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| 引用本文： | 齐志华,王海峰.一种嵌入式二乘二取二容错计算机联锁系统设计[J].北京交通大学学报(自然科学版),2006,30(5):96-100. |
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| 作者姓名： | 齐志华 王海峰 |
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| 作者单位： | 北京交通大学电子信息工程学院,北京,100044;北京交通大学电子信息工程学院,北京,100044 |
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| 基金项目： | 致谢：感谢铁道部运输局基础部信号处刘胜利高工对文章结构和系统设计所给予的建议与指导. |
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| 摘 要： | 基于嵌入式系统理论和容错系统体系结构,结合故障-安全电路的设计理念,给出了一种嵌入式二乘二取二容错计算机联锁系统的硬件设计.深入阐述了系统硬件电路的设计理论依据和工作原理,同时给出了设计中的元件选型.通过功能测试,系统设计符合故障-安全的设计原则,理论计算表明,其可靠性、安全性达到铁路信号系统要求.
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| 关 键 词： | 计算机联锁系统 故障-安全 容错 嵌入式系统 |
| 文章编号： | 1673-0291（2006）05-0096-05 |
| 收稿时间： | 2006-01-06 |
| 修稿时间： | 2006-01-06 |
Design of An Embedded Double 2-VOTE-2 Fault Tolerant Computer-Based Interlocking System |
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| QI Zhi-Hua,WANG Hai-feng.Design of An Embedded Double 2-VOTE-2 Fault Tolerant Computer-Based Interlocking System[J].JOURNAL OF BEIJING JIAOTONG UNIVERSITY,2006,30(5):96-100. |
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| Authors: | QI Zhi-Hua WANG Hai-feng |
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| Institution: | School of Electronics and Information Engineering, Beijing Jiaotong University, Beijing 100044 ,China |
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| Abstract: | Based on embedded system theory, fault tolerant and fail-safe principle, the paper presents an embedded hardware design with double 2-vote-2 fault tolerant architecture. Theory gists and operation principle of the design are discussed in detail. As well, the types of correlative component are also expounded. The results from function testing and theoretics calculation show that system design corresponds to fail-safe principle, the reliability and safety of system reach the railway signal system requirements. |
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| Keywords: | computer-based interlocking system fail-safe fault tolerance embedded system |
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