| USB3.0头包信息中CRC-16的Verilog实现 |
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| 引用本文： | 吴从中,尹夕振,彭乐.USB3.0头包信息中CRC-16的Verilog实现[J].合肥工业大学学报(自然科学版),2012,35(5):632-635. |
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| 作者姓名： | 吴从中 尹夕振 彭乐 |
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| 作者单位： | 合肥工业大学 计算机与信息学院,安徽 合肥,230009 |
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| 基金项目： | 中央高校基本科研业务费专项资金资助项目 |
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| 摘 要： | 文章基于CRC检错原理,根据USB3.0协议规定的要求,通过Verilog实现了一种并行的CRC-16的计算方法,设计模块在Quartus中编译和仿真,给出了电路实现结构图、模块的接口信号、信号的物理意义以及部分程序和仿真波形图,并将实验结果与USB3.0规范中给出的数据帧样本进行了比较。结果证明这种方法能完成USB3.0头包信息中CRC-16的计算,满足数据传输准确性和时序要求,并能用于USB3.0控制器包的产生模块和包的检测模块。
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| 关 键 词： | USB3.0协议 头包 Verilog语言 控制器 |
Verilog implementation of CRC-16 in USB3.0 packet header information |
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| WU Cong-zhong
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YIN Xi-zhen
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PENG Le.Verilog implementation of CRC-16 in USB3.0 packet header information[J].Journal of Hefei University of Technology(Natural Science),2012,35(5):632-635. |
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| Authors: | WU Cong-zhong YIN Xi-zhen PENG Le |
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| Institution: | (School of Computer and Information,Hefei University of Technology,Hefei 230009,China) |
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| Abstract: | Based on the CRC check principle,and according to the specified requirements of USB3.0 agreement,a parallel CRC-16 calculation method is implemented by Verilog language,and the design module is compiled and simulated in the Quartus.The circuit structure,interface signals of module,physical meanings of signals,partial programs and simulation waveform chart are presented,and the experimental results are compared with the sample data frames given by USB3.0 specification.The result proves that this method can complete the CRC-16 calculation of USB3.0 packet header information and meet the accuracy and time sequence requirements of the data transmission,so it can be used for the generation and checking modules of the packet of USB3.0 controller. |
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| Keywords: | USB3 0 agreement packet header Verilog language controller |
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