1.2 GSPS数字信道化接收机的设计与实现

在推导实信号数字信道化接收机高效结构的基础上,在硬件平台上完成了1.2 GSPS的16通道数字信道化接收机的实现。在FPGA实现中充分考虑了高速数据的可靠接收以及片内的数字处理速度和资源的优化,保证了系统良好的性能。实际中频测试结果表明,该数字信道化接收机的功能正确,性能稳定。

Design and implementation of a 1.2 GSPS digital channelized receiver

Based on the efficient structure of the real signal digital channelized receiver,a 1.2 GSPS receiver of 16 sub-channels is realized in hardware platform.In FPGA design,reliable receiving of high speed data as well as the processing speed and resource optimizing inside the chip are maturely considered to insure the good performance.The intermediate frequency test results of the receiver verify its correctness and stability.