基于扩展有限状态机和断言的总线接口协议测试平台

在SoC设计流程中，传统的仿真验证方法存在可观察及可控制性较差、自动化水平低等缺陷．为此，提出了一种基于扩展有限状态机（EFSM）和断言的SoC接口协议测试平台，该平台是一种自反馈测试平台，它不仅可以自动产生大量符合协议规范的测试激励矢量，而且可以通过对断言统计信息的反馈提供多种偏置选择，从而进一步提高验证的自动化水平．将该平台用于对视频后处理芯片中Wishbone总线接口协议的功能验证当中，验证结果表明，该平台可以缩短仿真验证时间大约55％～65％左右，有效地提高了验证的效率和质量．

Bus Interface Protocol Testbench Based on Extended Finite State Machine and Assertion

In SoC design flow, traditional simulation and verification have limitations such as invisibility, uncontrollability and low automation. An SoC interface protocol testbench based on the extended finite state machine （EFSM） and assertion was proposed. It was a self-reactive testbench, which could not only automatically generate massive protocol-compliant stimulus, but improve the simulation automation by providing numerous biasing options based on feedback on assertion statistical information. A verification experiment to Wishbone bus interface protocol of video post-processing chip was performed with this testbench. Experimental results show that this testbench can shorten simulation time by 55%-65%, and effectively improve the verification quality and efficiency.