亚毫微秒速度高均匀性多元逻辑电路的研制

就如何同时实现多元逻辑电路中线性“与或”门的高速和高均匀性进行了理论分析和实验验证，理论分析给出了平均延迟时间和均匀必的函数表达式；指出在影响电路速度和均匀性的诸多因素中，复合晶体管的发射结面积是一个关键因素，并依此进行了样品电路的优化设计和工艺制造，测试结果表明，单门平均延迟时间为0．22ns，功耗延迟积为0．55pJ，在输入一致条件下（0－4V），各单门电路之间输出不均匀性误差小于等于4mV。

High uniformity multicell-type logic (DYL) circuit with high speed of subnanosecond

How to accomplish the high speed and high uniformity of DYL at the meanwhile is discussed by theoretical analysis and experiment. The mathematical expression of the average delay and the uniformity is given. It indicates that arnong several factors affecting circult speed and uniformity the emitter junction area of the compond transistor is the key factor. The sample circuit is made by double ranges diffusion technique. The average delay per gate is 0. 22 ns and product of delay and power consumption is 0. 55 pJ. On the condition of identical input (0-4 V) the uniformity among each gate is less than or equal to 4 mV. The experiment results and theoretical analysis show that the DYL circuit is an excellent high speed and high uniformity linear logic switch gate.