高效低复杂度的QC-LDPC码全并行分层结构译码器

针对传统的部分并行结构低密度奇偶校验码(low-density parity-check codes,LDPC)译码器在保证较高吞吐量的同时,存在消耗硬件资源较大、迭代译码收敛速度较慢等问题,提出一种高效低复杂度的准循环低密度奇偶校验(quasi-cyclic low-density parity-check,QC-LDPC)码全并行分层结构译码器.这种改进的译码器结构可有效降低存储资源消耗,并克服并行处理所导致的访问冲突等问题.设计中,后验概率信息和信道初始化信息共用一个存储模块,降低了一半存储空间的占用.各个分层之间采用相对偏移的方式,实现了分层的全并行更新,提高了译码吞吐量.分层最小和译码算法(layered min-sum decoding algorithm,LMSDA)加速了译码迭代的收敛,进一步提高了吞吐量.经ISE 14.2软件仿真及Virtex7系列开发板验证的结果表明,当译码器工作频率为302.7 MHz、迭代次数为10的情况下,吞吐量可达473.2 Mbit/s,存储资源消耗仅为传统部分并行结构译码器的1/4.

Efficient low-complexity full-parallel-layered decoder for QC-LDPC codes

Aiming at the problem of too much hardware costs and slow convergence rates in traditional partial-parallel low-density parity-check ( LDPC) decoders with high throughput, a full-parallel-layered decoder for quasi-cyclic low-density parity-check ( QC-LDPC) codes with high efficiency and low complexity is proposed. The improved architecture of decoder can effectively reduce the memory resource consumption and overcome the problem of access conflict caused by the parallel processing. In this design, the posterior probability information and the channel initialization information share the same storage module, which reduce half of the storage space. The relative offset among the various layers is used for the full-par-allel-layered updating, which promotes the throughput. Moreover, the layered min-sum decoding algorithm ( LMSDA) ac-celerates the convergence of decoding iterations and further improves the throughput. By simulations on ISE 14.2 and valida-tions on Virtex 7 series board, it has been shown that the proposed decoder can achieve a throughput up to 473.2 Mbit/s when working on 302.7 MHz with 10 iterations. Moreover, the consumable memory resource accounts for only 1/4 of the traditional decoder.