| CMOS-DRAM的性能和设计 |
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| 引用本文： | 王嵩梅,徐葭生.CMOS-DRAM的性能和设计[J].清华大学学报(自然科学版),1988(1). |
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| 作者姓名： | 王嵩梅 徐葭生 |
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| 作者单位： | 微电子学研究所
(王嵩梅)，微电子学研究所(徐葭生) |
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| 摘 要： | 本文对近期发展起来的ＣＭＯＳ－ＤＲＡＭ的设计方案和性能优点进行了全面的分析。做在Ｎ阱内的单元阵列在抗α软失效方面有很大的好处。利用ＣＭＯＳ的特点使外围电路静态化既可以简化电路，又能提高电路速度和可靠性。对Ｓ／Ｒ放大器，时钟电路和行译码器等关键电路进行了较详细的分析，显示出ＣＭＯＳ－ＤＲＡＭ比ＮＭＯＳ－ＤＲＡＭ的优越性。
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| 关 键 词： | CMOS DRAM 静态 动态 |
The Performance and Design of CMOS-DRAM |
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| Wang Songmei,Xu Jiasheng.The Performance and Design of CMOS-DRAM[J].Journal of Tsinghua University(Science and Technology),1988(1). |
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| Authors: | Wang Songmei Xu Jiasheng |
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| Institution: | Institute of Microelectronics |
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| Abstract: | The design methodology and the advantages of performance of CMOSDRAM recently developed are discussed. Arranging the cell array in a N-well decreases the soft error rate. By means of CMOS circuits, the peripheral circuits can be made static, the whole circuits can be simplified, the speed and reliability can be raised. The key circuits, such as S/R amplifier, clock generator, row decoder and redundant circuits are analyzed in detail. The superiority of CMOS-DRAM over NMOS-DRAM is shown. |
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| Keywords: | CMOS DRAM static dynamic |
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