基于多相滤波的高精度延时设计及实现

雷达测距测速应用中的精确性取决于时间上的高分辨率, 而传统基于有限长单位冲激响应(finite impulse response, FIR)滤波的高精度延时设计所需的滤波阶数过高, 滤波处理较慢且复杂。为了加快滤波速度和节省硬件资源, 将数字内插与多相滤波技术结合, 提出了一种基于多相滤波的高精度延时设计方案。根据延时精度对FIR滤波系数向量重新排序, 依据延时量大小选择多相子滤波器对采样序列进行滤波处理, 实现小于整数倍采样间隔的高精度延时, 具有滤波速度快、节省硬件资源的特点。仿真分析延时信号的相位, 表明了所提多相滤波方案可实现高精度延时。借助现场可编程逻辑门阵列(field programmable gate array, FPGA)平台, 时钟频率为245.76 MHz时, 实测的延时精度可低至0.509 ns。

Design and implementation of high precision delay based on polyphase filtering

The accuracy in the radar ranging and speed application depends on the high precision of the time. High precision delay design, based on conventional finite impulse response (FIR) filtering, the required number of filter order is too high, and the filtering treatment is slower and more complicated. In order to speed up filtering and save hardware resources, this paper proposes a high precision delay design by combining digital interpolation with polyphase filtering. The FIR filter coefficient vector is reordered by the precision of time delay, and the polyphase filter is selected to filter the sampling data according to the size of the delay amount, so as to realize the high-precision delay less than the integer times of sampling period, which has the characteristics of fast filtering speed and high delay precision.The simulation results show that the proposed polyphase filter scheme can realize high precision delay by analyzing the phase of delay signal. With the field programmable gate array (FPGA) platform, the delay accuracy can be as low as 0.509 ns when the clock frequency is 245.76 MHz.