首页 | 本学科首页   官方微博 | 高级检索  
     检索      

一种基于累积分布函数的抖动测量方法
引用本文:郭健,冯建华,叶红飞.一种基于累积分布函数的抖动测量方法[J].北京大学学报(自然科学版),2012(3):381-385.
作者姓名:郭健  冯建华  叶红飞
作者单位:1. 北京大学微电子学系,北京100871
2. 北京大学深圳研究生院集成微系统科学工程与应用重点实验室,深圳518055 E-mail: fengjh@pku.edu.cn
基金项目:国家自然科学基金(90207018,60576030);国家科技重大专项(2009ZX02027)资助
摘    要:提出一种基于累积分布函数(CDF)的抖动测量方法,以解决在测试高频时钟信号抖动中遇到的延迟器件不匹配、占用芯片面积过大和受高频振荡信号限制等问题。采用65 nm CMOS工艺完成了测试电路的设计和功能模拟,模拟结果表明该电路可用于测量2.5 GHz时钟抖动值,抖动测量精度达到1 ps。

关 键 词:时钟抖动  内建抖动测试  时间数字转换器

A New On-Chip Jitter Measurement Method Based on Cumulative Distribution Function
GUO Jian,FENG Jianhua,YE Hongfei.A New On-Chip Jitter Measurement Method Based on Cumulative Distribution Function[J].Acta Scientiarum Naturalium Universitatis Pekinensis,2012(3):381-385.
Authors:GUO Jian  FENG Jianhua  YE Hongfei
Institution:1.Department of Microelectronics,Peking University,Beijing 100871;2.Key Laboratory of Integrated Microsystem Science Engineering and Applications,Shenzhen Graduate School of Peking University,Shenzhen 518055;
Abstract:The authors present a new on-chip jitter measurement method based on cumulative distribution function(CDF) to solve the problem of the mismatch of the delay line,taking up too much chip area and limited by high frequency oscillator signal,which are encountered in measuring multi-GHz clock jitter.The complete circuit is designed and implemented based on the 65 nm CMOS process.The simulation results show that the circuit is able to operate at 2.5 GHz and achieves a timing resolution up to 1 ps.
Keywords:timing jitter  built-in jitter measurement(BIJM)  time-to-digital(TDC)
本文献已被 CNKI 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号