高速低复杂度并行盲均衡的研究与FPGA实现

针对高速解调系统中由多径效应、射频器件和模数转换（ADC）的带内幅度相位的不一致性以及定时采样时刻的偏差等所引起码间串扰问题，提出了一种基于恒模算法（CMA）的低复杂度并行盲均衡实现结构，该结构运用弛豫超前变换技术以及快速FIR算法（FFA），在符号速率远高于FPGA时钟频率的情况下，通过运用低复杂度的流水线并行结构，以较少的硬件开销，满足盲均衡最大化数据吞吐量的要求.将本架构在Xilinx XC7VX690T硬件平台上实现，并应用于600 Ms/s符号速率的高速解调系统中，极大地提高了信号的质量，从而验证了本算法的可行性和高效性. 

Research on High Speed and Hardware Efficient Parallel Blind Equalization and Its FPGA Implementation

Aiming at the inter-symbol interference (ISI) caused by the multi-path interference, the inconsistency of the in-band amplitude phase of the RF device and the ADC, and the deviation of the timing sampling time in the high-speed demodulation system, a hardware efficient parallel blind equalization was proposed based on constant model arithmetic (CMA). The structure was designed with the relaxed look-ahead technique and the fast FIR algorithm. In the case where the symbol rate is much higher than the FPGA clock frequency, the blind equalization maximizes the data throughput requirements with less hardware cost by using a low complexity pipelined parallel structure. The architecture is implemented on the Xilinx XC7VX690T hardware platform and applied to the high-speed demodulation system with 600 Ms/s symbol rate, which greatly improves the quality of the signal, thus verifying the feasibility and efficiency of the algorithm.