| STD总线技术性能瓶颈分析 |
| |
| 引用本文： | 田俊峰,刘玉玲.STD总线技术性能瓶颈分析[J].河北大学学报(自然科学版),1995(4). |
| |
| 作者姓名： | 田俊峰 刘玉玲 |
| |
| 作者单位： | 电子与信息工程系 |
| |
| 摘 要： | 本文通过分析，得出了传统ＳＴＤ总线系统的性能特性之数学模型。验证了经验结论和实验结果。为突破ＳＴＤ总线瓶颈提供了依据，并由此提出了一种带逻辑ＣＰＵ的紧耦合多微处理器系统结构作为突破ＳＴＤ总线性能瓶颈的方案，并对其可行性作了简要分析。
|
| 关 键 词： | STD总线 性能瓶颈 多处理机系统 |
STDBUS Tecbnology Performance Bottole-neck Analysis |
| |
| Tian Jun feng, Liu Yuling.STDBUS Tecbnology Performance Bottole-neck Analysis[J].Journal of Hebei University (Natural Science Edition),1995(4). |
| |
| Authors: | Tian Jun feng Liu Yuling |
| |
| Abstract: | A mathmatical model for the characteristics of traditional STD BUS system has been obtained in this article. The experiential conclusions and experimental results have been tested and vertified. The basis is provided to break through the bottle-neck of STD BUS. A tight coupled multi-microprocessor system structure with legical CPU is advanced as the plan to break through performance bottle-neck of STD BUS. Its feasibility is simply analysed . |
| |
| Keywords: | STDBUS Perfomance Bottole-neck Multiprocessor System |
| 本文献已被 CNKI 等数据库收录！ |
