基于混沌的公开可验证FPGA知识产权核水印检测方案

现有的FPGA知识产权核(intellectual property,IP)水印技术在公开验证时可能会泄漏敏感信息,使得恶意的验证者或者第三方很容易将水印从IP中移除然后重新出售.零知识FPGA IP水印检测虽能有效的解决敏感信息泄露问题,但易遭受嵌入攻击,使得公开验证时无法防止非诚实IP购买者(验证者)抵赖侵权.本文提出一种新的基于混沌的公开可验证IP水印检测方案,不仅能防止敏感信息泄漏,而且能抵抗嵌入攻击,防止证明者、验证者或者可信第三方的欺骗.传统的FPGA IP水印技术,水印隐藏在未使用的Slice中,因此资源开销与水印嵌入数量成正比.而本文提出的方案中,水印隐藏在已经使用的Slice的未用的查找表(lookup table,LUT)中,资源和时延开销为0;此外,混沌系统具有良好的随机统计特性且对初值敏感、易于产生数量众多的互相关性极低的伪随机数序列,混沌系统的这些优点刚好满足方案中对FPGA位流文件的LUT随机位置置换的特殊要求,使得位置置换具有极高鲁棒性;最后,引入时间戳机制来抵抗嵌入攻击以防止非诚实的IP购买者抵赖.实验结果和分析表明本文提出的方案在水印开销和位置置换鲁棒性方面均明显优于现有的方案.

A chaotic-based publicly verifiable FPGA IP watermark detection scheme

IP （intellectual property） infringement has been a serious problem to FPGA vendors or IP designer. Watermarking is a novel technique for FPGA IP protection, while existing FPGA watermarking techniques may give away sensitive information during the public verification （e.g. the content or position of watermarks）, which enables malicious verifiers or third parties to remove the watermarks and resell the design. Existing zero-knowledge watermarking verification schemes are able to address the sensitive information leakage issue but are vulnerable to embedding attacks, which makes it ineffective in preventing denying infringement of un-trusted buyers （verifiers）. This paper presents a new chaotic-based publicly verifiable zero knowledge watermark detection scheme for FPGA IP protection. This scheme is both resilient against the sensitive information leakage issue and removing attacks, thus robust to cheating from provers~ verifiers or the third party. In traditional FFGA watermarking techniques, watermarks are embedded in the used Slices, thus the area overhead is proportional to the number of embedded watermarks, hi tim proposed scheme, watermarks are hidden in the unused LUTs of used Slices, introducing zero area and timing overheads. Chaotic systems are sensitive to initial values and convenient to produce numerous pseudo-random numbers with ultra-low coefficients and perfect statistical property. These advantages match the specific requirements for the random location permutation of the LUTs ill tile FPGA bit-stream file in the zero knowledge protocol, bringing an ultra-high robustness of LUT location permutation. The tinlestalnp mechanism is also introduced in this paper to resist embedding attacks against denying the infringement from un-trusted IP buyers （verifiers）. Experimental results and analysis show that the proposed scheme is significantly better than the latest related literatures in both watermarking overheads and robustness of location permutation.