集成电路电磁适应性的时钟信号调制

电磁干扰(EMI)是瞬时功能故障的主要来源之一,原因是电源供电线上的噪声注入引起了VDD和GND的额定值的波动.介绍了一种新的方法来增强片上系统(SoC)关于电源和接地电压瞬变时的信号完整性,并且这种方法完全符合IEC 61000-4-29 标准.其基本思想是设计和IEC 61000-4-29兼容的集成电路,通过局部和动态地将时钟占空比去适应传播延迟的变化和扰动的逻辑路径.当无法满足时,该方法导致暂时把集成电路的工作频率减小到满足该标准的最小值.根据异常电网活动,时钟占空比调制(CDCM)是通过使用正和/或负边沿时钟展宽逻辑(CSL)块来实现的.基于这个概念,在尽可能保持时钟高速频率的同时,数字电路对于电源供电线上波动的耐受性将会更强.该方法可被视作一种在线提供动态自适应同步的监视技术.通过SPICE模拟,实验结果表明此方法的有效性.

Clock signal modulation for IC electromagnetic compatibility

Electromagnetic Interference(EMI)is one of the main sources of transient functional failure due to noise injection on power supply lines,which induces fluctuations on VDD and Gnd nominal values.This paper presents a new methodology to enhance System on Chip(SoC)signal integrity with respect to power/ground voltage transients,fully compliant with this IEC 61000-4-29 standard.The underlying idea is to design IEC 61000-4-29 compatible Ics by locally and dynamically adapting the Clock Duty-Cycle(CDC)to the variation of propagation delays along with the disturbed logic paths.In case this is not possible,the methodology leads to a temporary reduction of the IC operating frequency to the minimum value that satisfies such standard.According to abnormal power grid activity,CDC modulation(CDCM)is achieved by using positive and/or negative edge Clock Stretching Logic(CSL)blocks.Based on this concept,digital circuits become more robust to power line fluctuations while maintaining at-speed clock rate if possible.The methodology may be viewed as an on-line supply monitoring technique with dynamic adaptive synchronism.Experimental results obtained throughout SPICE simulations have been used to demonstrate the proposed methodology.