| 基于FPGA的并行FIR数字滤波器硬件实现及优化 |
| |
| 引用本文： | 付正,郑维智,江远志. 基于FPGA的并行FIR数字滤波器硬件实现及优化[J]. 北京工商大学学报(自然科学版), 2010, 28(5): 69-74 |
| |
| 作者姓名： | 付正 郑维智 江远志 |
| |
| 作者单位： | 北京工商大学,机械工程学院,北京,100048 |
| |
| 基金项目： | 北京市教育委员会科技计划项目(KM200810011007) |
| |
| 摘 要： | 阐述了基于有限脉冲响应数字滤波器FIR的可编程逻辑器硬件实现的优化和改进方案.介绍了FIR滤波器原理及传统线性FIR滤波器的实现结构,提出了并行FIR滤波器的结构改进思路,详细地说明了各模块具体功能的实现及采用技术,最后给出了并行FIR的拓展应用方案.
|
| 关 键 词： | 现场可编程逻辑器件 硬件描述语言 Max-plusⅡ 有限脉冲响应数字滤波器 |
HARDWARE IMPLEMENTATION'S OPTIMIZATION OF FPGA-BASED PARALLEL FIR DIGITAL FILTERS |
| |
| FU Zheng,ZHENG Wei-zhi and JIANG Yuan-zhi. HARDWARE IMPLEMENTATION'S OPTIMIZATION OF FPGA-BASED PARALLEL FIR DIGITAL FILTERS[J]. Journal of Beijing Technology and Business University:Natural Science Edition, 2010, 28(5): 69-74 |
| |
| Authors: | FU Zheng ZHENG Wei-zhi JIANG Yuan-zhi |
| |
| Affiliation: | FU Zheng,ZHENG Wei-zhi,JIANG Yuan-zhi(College of Mechanical Engineering,Beijing Technology , Business University,Beijing 100048,China) |
| |
| Abstract: | The hardware implementation and optimization and improvement proposal for FPGA-based Parallel FIR digital filters were detailed in this paper.The principle of FIR filter and the implementation structure of traditional linear FIR filter were introduced,and thoughts of optimization and improvement for Parallel FIR digital filters were proposed.Each module's specific functions and technology were set out,and parallel FIR digital filters' expansion applications were then put forward. |
| |
| Keywords: | FPGA VHDL Max-Plus Ⅱ FIR |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
| 点击此处可从《北京工商大学学报(自然科学版)》浏览原始摘要信息 |
|
点击此处可从《北京工商大学学报(自然科学版)》下载全文 |
|
