| 32位并行浮点乘法器设计 |
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| 引用本文： | 张菁.32位并行浮点乘法器设计[J].南京邮电大学学报(自然科学版),2009,9(21). |
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| 作者姓名： | 张菁 |
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| 摘 要： | 本文讨论了32位浮点乘法器的设计，算法采取了二阶Booth算法；部分积产生阵列采用了由反极性CSA加法器组成的IA与wallace树折衷方法；最后并给出了设计结果与验证。
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| 关 键 词： | Booth算法 4∶2压缩器 Wallace树 |
Design of Floating-point 32 bit Parallel Multiplier |
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| zhang jing.Design of Floating-point 32 bit Parallel Multiplier[J].Journal of Nanjing University of Posts and Telecommunications,2009,9(21). |
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| Authors: | zhang jing |
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| Abstract: | This paper design a 32 bit float multiplier. 2-steps booth algorithm be used and adopt Iterative array and Wallace-tree structure which are composed of inverse polarity CSA adders to create partial product. At last we give the result of design and verification. |
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