| 基于有限状态机的数字同步重频分选器 |
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| 引用本文： | 张欣. 基于有限状态机的数字同步重频分选器[J]. 系统工程与电子技术, 2001, 23(3): 31-33 |
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| 作者姓名： | 张欣 |
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| 作者单位： | 成都雷通电子系统有限公司ASIC设计中心, |
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| 摘 要： | 针对FPGA/CPLD芯片设计中常常会遇到脉宽识别的问题,根据实际工程设计了一种同步重频分选器,它在某些通讯系统中有极其重要的应用。主要介绍如何通过同步有限状态机来设计该数字重频分选器,结合CPLD芯片的设计,给出了它的具体设计思想,以及VHDL语言描述的有限状态机的源代码、逻辑综合、时序仿真结果。
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| 关 键 词： | 脉冲信号 重复频率 芯片 信号处理 |
| 文章编号： | 1001-506X(2001)03-0031-03 |
| 修稿时间： | 1999-11-06 |
Digital SynchronousRepetition Rate Separation on FSM |
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| Zhang Xin. Digital SynchronousRepetition Rate Separation on FSM[J]. System Engineering and Electronics, 2001, 23(3): 31-33 |
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| Authors: | Zhang Xin |
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| Affiliation: | Zhang Xin Chengdu Raytong Electron System Ltd.ASIC Design Center,610041 |
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| Abstract: | A Synchronization repetition rate separation chip is established for engineering according to the question of pulse width recognition in design of FPGA/CPLD Chips. And is has significant application in some communication systems. This paper introduces the theory of synchronous repetiton rate separation, presents source code program of finite-state machine (FSM) of VHSIC hardware description language(VHDL), the results of logic synthesize, and timing simulator.; |
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| Keywords: | Pulse signal Repeating frequency Chip Information processing |
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