| eDRAM高速读写和紧凑式电荷转移刷新方案 |
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| 引用本文： | 程宽,马亚楠,孟超,董存霖,林殷茵.eDRAM高速读写和紧凑式电荷转移刷新方案[J].复旦学报(自然科学版),2012,51(1):33-42. |
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| 作者姓名： | 程宽 马亚楠 孟超 董存霖 林殷茵 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室,上海,201203 |
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| 摘 要： | 提出了一种采用逻辑工艺、访存速度优化、降低刷新功耗的动态随机存储器（DRAM）,使其在嵌入式系统的设计与制造中易于与高性能逻辑电路融合.采用读写前置放大的高速读写方案,使DRAM读写速度得到了优化;采用紧凑式电荷转移刷新替代传统刷新方案,在降低了刷新功耗的同时,缩短了DRAM的刷新时间开销,提高了DRAM的数据可访问性...
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| 关 键 词： | 动态随机存储器 逻辑工艺 高速读写 紧凑式电荷转移刷新 |
An eDRAM with Logic Technology Using High-Speed R/W and Compact Charge Transfer Refresh Scheme |
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| CHENG Kuan,MA Ya-nan,MENG Chao,DONG Cun-lin,LIN Yin-yin.An eDRAM with Logic Technology Using High-Speed R/W and Compact Charge Transfer Refresh Scheme[J].Journal of Fudan University(Natural Science),2012,51(1):33-42. |
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| Authors: | CHENG Kuan MA Ya-nan MENG Chao DONG Cun-lin LIN Yin-yin |
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| Institution: | (State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China) |
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| Abstract: | An embedded DRAM with logic technology using high-speed read/write and low power refresh scheme is proposed.The logic technology enables DRAM easier to merge with high performance logic circuits in design and fabrication of embedded systems.Adopting read/write pre-amplifier scheme optimizes the operation speed of the memory.Compact charge transfer refresh is used to replace conventional scheme so as to reduce the refreshing power and time of the memory,thus the data availability of DRAM is improved.With 3ns clock cycle,the simulation results illustrate that the write cycle of memory is 3 ns and is 23% reduced,meanwhile the access time is 1.8 ns and is 15% reduced,compared with the conventional scheme.The refreshing power and time are 58% and 43% reduced respectively,compared with the conventional scheme. |
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| Keywords: | DRAM logic technology high-speed read write compact charge transfer refresh |
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