| FIDER： A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan |
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| 引用本文： | 王云峰,边计年,洪先龙,周强,吴强.FIDER： A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan[J].清华大学学报,2007,12(1):63-69. |
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| 作者姓名： | 王云峰 边计年 洪先龙 周强 吴强 |
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| 作者单位： | Department of Computer Science and Technology Tsinghua University，Department of Computer Science and Technology Tsinghua University，Department of Computer Science and Technology Tsinghua University，Department of Computer Science and Technology Tsinghua University，Department of Computer Science and Technology Tsinghua University，Beijing 100084 China，Beijing 100084 China，Beijing 100084 China，Beijing 100084 China，Beijing 100084 China |
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| 摘 要： | As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.
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| 关 键 词： | 集成电路 平面布局图 内部连线延迟 数据通路 优化 力平衡再合成算法 FIDER |
| 收稿时间： | 14 November 2005 |
| 修稿时间： | 2005-11-142006-02-16 |
FIDER: A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan |
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| WANG Yunfeng,BIAN Jinian,HONG Xianlong,ZHOU Qiang,WU Qiang.FIDER: A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan[J].Tsinghua Science and Technology,2007,12(1):63-69. |
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| Authors: | WANG Yunfeng BIAN Jinian HONG Xianlong ZHOU Qiang WU Qiang |
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| Institution: | Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China |
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| Abstract: | As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance. |
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| Keywords: | high-level synthesis floorplan interconnect delay re-synthesis reschedule reallocation |
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