| 伪随机序列捷变频跳频频率合成器的研制 |
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| 引用本文： | 郭德淳,费元春. 伪随机序列捷变频跳频频率合成器的研制[J]. 北京理工大学学报, 2001, 21(6): 753-756 |
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| 作者姓名： | 郭德淳 费元春 |
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| 作者单位： | 北京理工大学,电子工程系,;北京理工大学,电子工程系, |
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| 摘 要： | 研究一种跳频通信机低杂散、低相噪快速捷变频率合成器的实现途径。该合成器采用DDS芯片（AD9852）激励PLL（Q3236）的方案,控制单元采用TI公司的DSP芯片TMS320C31,将DDS极高的频率分辨力与锁相式频率合成器较高的工作频率结合起来,获得了更高的频率合成性能,其主要技术指标为：相位噪声小于-100dB/Hz（偏离载频1kHz处）,杂散电平小于-60dB。
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| 关 键 词： | 直接数字频率合成器 锁相环 跳频 伪随机序列 |
| 文章编号： | 1001-0645(2001)06-0753-04 |
| 修稿时间： | 2001-04-06 |
Development of Pseudorandom Sequence Agile Frequency Hopping Frequency Synthesizer |
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| GUO De chun,FEI Yuan chun. Development of Pseudorandom Sequence Agile Frequency Hopping Frequency Synthesizer[J]. Journal of Beijing Institute of Technology(Natural Science Edition), 2001, 21(6): 753-756 |
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| Authors: | GUO De chun FEI Yuan chun |
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| Abstract: | An approach of a low spurious, low phase noise, agile frequency synthesizer was presented. The synthesizer adopted DDS chip (AD9852) as the excitation for the PLL chip (Q3236) and TMS320C31 of TI as its control unit. By combining the lutra high frequency resolution of DDS and the high operation frequency of PLL, better performance can be achieved. The phase noise of the synthesizer output is less than -100 dB/Hz(away from carrier 1 kHz) and the spurious level is less than -60 dB. |
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| Keywords: | direct digital frequenecy synthesizer PLL frequency hopping pseudorandom sequence |
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