| 大规模集成电路多层布线结构对信号延时的影响 |
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| 引用本文： | 刘峰,梁勇强. 大规模集成电路多层布线结构对信号延时的影响[J]. 玉林师范学院学报, 2004, 25(5): 45-48 |
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| 作者姓名： | 刘峰 梁勇强 |
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| 作者单位： | 1. 玉林师范学院,职业技术学院,工程师,讲师,广西,玉林,537000
2. 玉林师范学院,职业技术学院,工程师,广西,玉林,537000 |
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| 摘 要： | 通过集成电路各器件间的布线传递信号的过程，是将信号电荷向布线间形成的寄生电容充放电的过程。本文研究了集成电路多层连线的寄生电容模型、互连线RC树模型的延时估算等电路模拟技术，同时提出了今后该领域的研究方向。
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| 关 键 词： | 多层布线 延时 寄生电容 |
| 文章编号： | 1004-4671(2004)05-0045-04 |
| 修稿时间： | 2004-06-28 |
The Influence of the Multi-Layer Cabling Structure in Integrated Circuit on the Signal Delay |
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| LIU Feng,LIANG Yong-qiang. The Influence of the Multi-Layer Cabling Structure in Integrated Circuit on the Signal Delay[J]. Journal of Yulin Teachers College, 2004, 25(5): 45-48 |
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| Authors: | LIU Feng LIANG Yong-qiang |
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| Affiliation: | LIU Feng1,LIANG Yong-qiang2 |
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| Abstract: | Electricity charges and discharges from the multi-layer cabling's parasitic capacitance when signal is transferred among different parts of integrated circuit.This paper analyses the parasitic capacitance's pattern of multi-layer cabling and delay estimation of cabling's RC tree,and puts forward research orientations in this domain. |
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| Keywords: | multi-layer cabling delay parasitic capacitance |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
