低资源消耗多边类型LDPC码译码器的FPGA实现

以低资源消耗和低功耗应用为基础设计了多边类型低密度奇偶校验码译码器. 该译码器采用缓存有效连通校验点计算单元与变量点计算单元. 分析和实验表明，与传统的部分并行译码器结构相比，若校验矩阵不具有特殊结构，该译码器可以减少近50% 的用于存储迭代信息的存储器；节约近90% 的用于传输迭代信息的多路选择器；节省80% 的变量点计算单元.

Decoder with Low Resource Overhead for Multi-edge Type LDPC Codes Based on Cache

To study low cost and low power applications, we propose a decoding architecture with low resource overhead for multi-edge-type low density parity check (LDPC) codes. The architecture links the check node computed unit and variable node computed unit by cache. The analysis and experiments show that, compared with the traditional partial parallel decoding architecture, the decoding architecture described in this paper cuts about 50% RAM for storing iterative information when the check matrix is random, about 90% MUX for transmitting iterative information, and about 80% variable node computation unit for generating iterative information transmitted form variable nodes to check nodes.