一种有效的性能驱动布图算法

提出了一种有效的性能驱动布局和布线算法。算法自始至终考虑互连线延时对芯片时间性能的影响，以优化芯片时间性能为主要布图目标，并兼顾布线均匀和连线总长最短。算法利用选定的单元、互连线延时计算模型以及关键路径识别算法对整个芯片进行动态的延时分析，并由此得出线网（亦称互连线）权重信息以指导迭代改善布局和布线，达到优化芯片时间性能的目的。运行实例表明本算法是正确、有效的。

An efficient performance-driven layout algorithm

In this paper, an efficient performance-driven placement and routing algorithm isproposed. During each process the interconnection delays are modeled and considered in order to improve the chip timing performance. Our objective function mainly aims at minimizing the longest path delay of the chip and also aims at improving the total wire length and theeven distribution of wiring. In this algorithm, a timing analysis package composed of delaycalculation model and critical path recognition is established. During the iterative improvements of placement and routing, timing analysis is used dynamically in order to modify thenet's weight. By using the information of net's weight the timing performance of the layoutcan be improved. The experimental results show that the algorithm proposed is correct andefficient.