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基于FPGA面向多媒体处理的MPSoC
引用本文:李晶皎,陆振林,王爱侠,王骄. 基于FPGA面向多媒体处理的MPSoC[J]. 东北大学学报(自然科学版), 2012, 33(4): 486-490. DOI: -
作者姓名:李晶皎  陆振林  王爱侠  王骄
作者单位:1.东北大学信息科学与工程学院,辽宁沈阳,110819;2.东北大学信息科学与工程学院,辽宁沈阳,110819;3.东北大学信息科学与工程学院,辽宁沈阳,110819;4.东北大学信息科学与工程学院,辽宁沈阳,110819
基金项目:国家自然科学基金资助项目,辽宁省博士启动基金资助项目
摘    要:针对嵌入式单核处理器处理速度慢及主频提升受限等问题,提出了嵌入式双核处理器(two-cores embedded processor,TEP)模型.针对处理器运行时对存储器的依赖和分配问题,提出了基于非统一存储结构模拟分布式存储结构的方案;针对多核间对共享数据存储器的访存问题,给出了从属单元的仲裁机制,实现了共享资源的访问;针对面向多媒体应用的多核处理器间传输数据量大及通讯开销高的问题,提出了基于消息数据分离的传输方案.系统在FPGA平台进行了实现和验证,测试结果表明,TEP系统以较少的资源消耗和通讯开销获得了大加速比的性能.

关 键 词:片上多处理器  嵌入式双核处理器  非统一存储结构  FPGA  消息数据分离  

FPGA Based MPSoC for Multimedia Processing
LI Jing-jiao,LU Zhen-lin,WANG Ai-xia,WANG Jiao. FPGA Based MPSoC for Multimedia Processing[J]. Journal of Northeastern University(Natural Science), 2012, 33(4): 486-490. DOI: -
Authors:LI Jing-jiao  LU Zhen-lin  WANG Ai-xia  WANG Jiao
Affiliation:(School of Information Science & Engineering,Northeastern University,Shenyang 110819,China.)
Abstract:A two-cores embedded processor(TEP) model was proposed to overcome the problems of slow processing speed and the limited main frequency ascension of the embedded mononuclear processor.On the basis of the nonuniform storage structure,the simulated distributed storage structure was presented to solve reliance and distribution of memory when the processor is running.The arbitration mechanism of the subordinate unit was proposed to realize the access of sharing resources for the accessing memory problem of the share data storage among multiple processors.On the basis of the separation of the message data,a kind of data transmission scheme was proposed to overcome a large number of the data transmission and the higher communication spending of the multiple processors facing the multimedia applications.The system was realized and verified on the FPGA platform,which indicated that TEP got a good performance on accelerator with less resource/transmission spending.
Keywords:MPSoC(multiple processor system on chip)  TEP(two-cores embedded processor)  nonuniform storage structure  FPGA(field programmable gate array)  message and data separation
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