基于逻辑函数的电路可测性设计及多故障测试

逻辑函数可以根据需要被表示成多种不同的形式,其中的ESOP形式所需积项较少且具有一般性.针对数字电路的多故障,基于逻辑函数的ESOP形式,采用与门阵列和异或门树来进行电路的可测性设计,提出了在这种电路结构下的多故障测试方法,给出了检测电路中多故障的通用测试集.该测试集可从电路结构图直观求得,无需进行复杂处理,从而使测试生成变得简单快捷.

Multiple Fault Detection for Easily Testable Realizations of Logic Functions

The EXOR sum of products (ESOP) is the most general form of 2 level AND EXOR networks, it usually requires fewer products than Reed Muller canonic expressions. A new method of design for testability (DFT) is presented in the paper, which employs AND gates and XOR gates tree to realize the ESOP expression of arbitrary logic functions. The method is able to reduce the delay in the circuits as compared with the approaches using XOR gates cascade. A universal test set which detects multiple faults in the circuit realization is given, it can be generated easily and is independent of the logic function realized. The results have considerable significance on the detection and testable design of multiple faults in the digital circuits.