一种面向输入缓冲交换机的多VC共享预取结构

针对目前交换机的输入缓冲区读延迟增大导致交叉开关吞吐率下降的问题，提出了多VC共享预取结构SPB，用于隐藏数据缓冲区SRAM的读延迟.设计了旁路写入控制、读写地址管理、预取管理等关键功能，用Verilog语言实现了SPB结构，通过模拟器测试了SPB结构的读写性能.模拟和分析结果表明，采用SPB结构的输入缓冲区能够降低读写延迟，提高输入缓冲区的写入和读出吞吐率.SPB结构能够被方便地应用于静态分配多队列或动态分配多队列缓冲区中，加快缓冲区的读写速度，从而提高整个交换机的吞吐率.

A Multi-VC Shared Prefetch Structure for Input-buffered Switch

At present, the read latency of input buffer in switch is increasing, which greatly decreases the throughput of crossbar. To address this issue, a multi-VC shared prefetch structure was proposed in order to hide the read latency of data buffer implemented by SRAM with registered output. Some critical functions of SPB were designed, such as bypass write control, the management of write and read address, prefetch control, etc. Moreover, the SPB structure was implemented in Verilog and its performance was tested by cycle accurate simulator. The simulation results and analysis show that input buffer with SPB structure will not only decrease the read and write latency but also increase the throughput of the input buffer. The SPB structure proposed can be used in combination with either SAMQ or DAMQ buffer to speed up the read and write operation of the buffer, and further improve the throughput of the whole switch.