高速同步总线的时序设计

从总线时间比的角度出发分析了总线时序实现的难易程度。通过对时间方程的分析 ,讨论了严格同步的时钟系统、固定相移的同步时钟系统、动态调节的同步时钟系统的总线时序 ,并设计出一种时钟相位可调总线时序。在此基础上实现了一种基于GTL逻辑的高速同步总线测试系统 ,并通过实际测试证明了对三种同步时钟系统总线时序分析的正确性 ,结论为各种实际高速同步总线的时序设计提供了很好的参考价值

Timing Design of High Speed Synchronous Bus

By analysis of bus timing ratio, the difficulty of realizing bus timing is discussed in this paper. Based on the timing equation, the authors probe into the bus timing of synchronous clock system, fixed skew synchronous clock system and dynamically adjusted skew synchronous clock system. In addition, the authors give a kind of bus timing with adjustable clock skew. At last, a testing system of high-speed synchronous bus is realized by using GTL logic, and test results match theoretical analysis of three kinds of synchronous clock system. The conclusion provides a valuable reference for real high-speed bus timing design of synchronous clock system.